ESMT M15T4G16256A (2P) Elite Semiconductor Microelectronics Technology Inc Publication Date: Jun. 2024 Revision: 1.1 1/173 DDR3(L) SDRAM 32M x 16 Bit x 8 Banks DDR3(L) SDRAM Feature VDD = VDDQ = 1.35V (1.283–1.45V) Backward-compatible to VDD = VDDQ = 1.5V ±0.075V Differential bidirectional data strobe 8n-bit prefetch architecture Differential clock inputs (CK, CK#) 8 internal banks Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals Programmable CAS (READ) latency (CL) Programmable posted CAS additive latency (AL) Programmable CAS (WRITE) latency (CWL) Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS]) Selectable BC4 or BL8 on-the-fly (OTF) Self refresh mode Self refresh temperature (SRT) Automatic self refresh (ASR) Write leveling Multipurpose register Output driver calibration
